1. Field of the Invention
The present invention relates to structures electrically connecting semiconductor metal interconnections and methods of forming the same, and more particularly, to structures electrically connecting aluminum and copper interconnections and methods of forming the same.
2. Description of Related Art
Typically, semiconductor devices have metal interconnections to electrically connect discrete semiconductor elements. The metal interconnections are formed to fill a contact hole penetrating a predetermined region of an interlayer insulating layer while crossing over the top surface of the interlayer insulating layer. The metal interconnections are formed of conductive material having a high current carrying capability. The metal interconnections may be formed by stacking aluminum (Al) and copper (Cu).
The aluminum and copper interconnections make the manufacturing environment in a semiconductor metallization process unstable by diffusing into one another. The semiconductor metallization process may be performed with a barrier pattern interposed between the aluminum interconnection and the copper interconnection so as to stabilize the manufacturing environment. Using the barrier pattern, the manufacturing environment becomes dependent on a shape of a barrier pattern shape. The aluminum and copper interconnections may contact each other depending on the shape of the barrier pattern.
A semiconductor device that is not dependent on the shape of the barrier pattern and a method of fabricating the semiconductor device are suggested by Matsunaga Noriaki, etc. in Japanese Laid-Open Patent Publication No. 2004-221118. According to Japanese Laid-Open Patent Publication No. 2004-221118, a lower interconnection is disposed on a semiconductor substrate, first and second insulating layers are sequentially formed on the lower interconnection, an interconnection hole exposing the lower interconnection is formed in the first and second insulating layers, and a barrier metal layer and via is deposited to fill the interconnection hole.
However, in the invention of Japanese Laid-Open Patent Publication No. 2004-221118, depending on the position of the interconnection hole in the semiconductor substrate, the lower interconnection and the via may come into direct contact at a bottom of the interconnection hole. This is because the interconnection hole may have different numbers of atoms supplied from a barrier metal source target during a semiconductor metallization process in order to form the barrier metal layer at the edge or central region of the semiconductor substrate. Therefore, the barrier metal layer in the interconnection hole may be partially cut off at the edge of the semiconductor substrate, thus allowing the via to directly contact the lower interconnection through the metal layer.
Therefore, a need exists for an interconnection in which an aluminum interconnection is formed not to directly contact a copper interconnection through the contact hole.